The eMMC memory device is the standard form of embedded NAND Flash in all smartphones, tablets, Chromebooks, and many other portable or stationary consumer electronics. Designed to be cost-effective and Linux based, this eMMC 5.1 hardware validation platform (HVP) consists of Arasan’s eMMC 5.1 IP mapped into FPGA’s, offering full-speed physical connectivity to a complementary SoC host or memory card device. Arasan’s active participation in the JEDEC/eMMC standards bodies and early customer engagement has made Arasan’s eMMC controller IP a reference in the industry.
An equally important part of the eMMC 5.1 HVP is the software stack, which abstracts all the low-level software drivers and hardware to a loadable shared object with easy to use API. Hence, an applications software, validation, or systems engineer does not need to delve into the protocol and signaling details and considers the Arasan platform as a programmable complementary device. The eMMC 5.1 HVP can be used by system developers, system integrators, software developers, and system quality analysts to debug as well as validate their products during the product life-cycle.
Features
Compliance
- Meets eMMC spec v 4.2/4.3/4.4/4.51/5.0/5.1
- eMMC Device Validation
- CRC7 and CRC16 Cyclic Redundancy Checks
- Supports Boot operations in Full speed, High speed, & DDR
- Supports 1/4/8-bit data transfers
- Supports HS200 tuning and HS400 operation capable of up to 3.2 Gbps
- Supports eMMC Field firmware update, device health report, production state awareness, & secure removal types
Deliverables
- SD/SDIO/eMMC Validation Platform including:
- SD 3.0/SDIO 3.0/eMMC 5.1 Controller IP implemented in FPGA
- SD Software Stack
- Linux Installer Package with Documentation
- Documentation
Benefits
- Early software development for Host-side application
- Ready to use platform for Device validation
- Popular Linux operating environment
- Silicon proven IP
Arasan’s general purpose I/O PADs are multipurpose PADs that can be programmed to operate in different modes: 1) Output with predetermined source/sink impedance, 2) Open drain, 3) Input, 4) Tristate and 5) Weak pull up or pull down. The I/O PADs are specially designed to seamlessly integrate with Arasan’s eMMC 5.1 and eMMC 5.0 host controller IP. Arasan introduced the industry’s first HS400PHY in 2013 on multiple nodes and since then the engineering team has been working diligently to keep up with the latest versions.