The MIPI CPHY V1.1 improves throughput over a bandwidth-limited channel, allowing more data without an increased signaling clock. It is intended to be used for camera interface (CSI-2 v1.3) and display interface (DSI-2 v1.0). The signaling interface uses a 3-phase transceiver that encodes 3-bit symbols over 3 wires. This is different from the two-wire differential “lane” used in D-PHY.
C-PHY was designed to coexist on the same IC pins as D-PHY so that dual-mode devices could be developed with low power signaling similar to DPHY. Arasan’s CPHY-DPHY combination provides a 3 channel MIPI CPHY v1.1.
Symbol encoding effectively transfers 2.286 bits per symbol compared to 1.0 bits per lane for D-PHY. This version of C-PHY (v1.1) operates at 2.5GHz(2.5GS/s), the same as the D-PHY V1.2(2.5Gb/s).
A 3 channel C-PHY provides 17Gbps which enables:
- 4K video at 60fps
1080p at 240fps (for cool slow-motion videos)
Diagram
Features
- Compliant to MIPI Alliance Standard for C-PHY specification Version 1.1
- Supports standard PHY transceiver compliant to MIPI Specification
- Supports standard PPI interface compliant to MIPI Specification
- Supports asynchronous transfer at high speed mode with a symbols rate of 80-2500 MS/s.
- Supports asynchronous transfer at low power mode with a bit rate of 10 Mb/s
- Spaced one hot encoding for Low power [LP] data
- Supports maximum of three data lanes.
- Supports error detection mechanism for sequence errors and contentions
- Data lanes support transfer of data in high speed mode.
- Supports ultra low power mode, high speed mode and control mode.
- Has clock divider unit to generate clock for parallel data reception and transmission from and to the PPI.
- Activates and disconnects high speed terminators for reception and transmission.
- On-chip clock generation configurable for transmitter.
Process & Foundry
- Available in various foundry processes
- No external (off-chip) components required
- Can be ported to other processes
Deliverables
- GDS-II Database
- LVS Netlist
- Physical Abstract Models (LEF)
- Timing Models (LIB)
- Process Specific Integration Guide
Benefits
- Silicon proven
- Extensive Quality Methodology